1. Field of the Invention
This invention relates generally to semiconductor processes for forming transistors and, more specifically, to processes for increasing layout density on a semiconductor substrate.
2. Description of the Related Art
Transistors such as planar transistors have been the core of integrated circuits for several decades. During the use of transistors, the size of the individual transistors has steadily decreased through advances in process development and the need to increase feature density. Current scaling employs 32 nm technologies with development progressing towards 22 nm technologies.
Metal 1 (M1) vertical wire routes used to connect between NMOS and PMOS structures are important in standard transistor cell designs. The M1 vertical wire routes may connect to contacts (outputs) that contact to active areas of the underlying layer. The M1 vertical wire routes may be in addition to other M1 wires that contact to gates.
A first challenge in routing M1 wires (either contact wires or vertical wires) is misalignment, or overlay error. Misalignment is an increasing challenge in modern lithography, which results in certain practical limitations. One practical limitation is that the offset between small contacting features is desired to be kept as small as possible with coinciding centers being preferred. Solving this limitation encourages, for example, that a contact is placed centered over a gate and a thin M1 wire is placed centered over the contact such that the gate, the contact, and the M1 wire are all centered over the same point.
A second challenge is the desire for CPP (contacted poly pitch) to be close to limits of technology (for example, 22 nm design rules). This desire makes it not possible to pattern an additional M1 wire (such as the vertical M1 wire) between two contacted gates when the M1 and the gates are concentric, which is preferred to avoid misalignment as described above. Being able to route the M1 vertical wire between the contacted gates while avoiding misalignment would allow a denser layout, resulting in a lower product cost and faster operation.
FIG. 1 depicts a top view of a device with a contact and a metal layer structure directly over a gate. Layout 100 includes gates 102A, 102B coupled to M1 structures 104A, 104B by contacts 106A, 106B, respectively. M1 structures 104A, 104B are input contacts for gates 102A, 102B. Because of the closeness of M1 structures 104A, 104B, there is no room between the M1 structures for another M1 structure such as an M1 vertical wire route. Area 108 represents the area around M1 structures 104A, 104B that is blocked for placement of other M1 structures due to the density of the layout.
One possible solution to allow for an M1 vertical wire route in layout 100 is to bloat the gate area (CPP bloat) by putting in a dummy gate to increase the horizontal distance between active gates. This method, however, increases the overall chip area and limits the performance of the chip versus chip area.
Another possible solution is to use an extra local interconnect (LI) layer to make the connection to the output instead of the M1 vertical wire route. The LI layer can be used for contacts to gates and/or contacts to active regions. However, the use of the LI layer requires the use of an additional via (V0) layer to inhibit shorting of the LI layer to nearby M1 wires. The additional V0 layer may significantly increase development and/or processing costs.
Another possible solution is to use a wrong way metal 2 (M2) layer where the M2 layer is exposed and the M2 wire in the same direction as the M1 wire. This makes it difficult to route wires from other locations (for example, other logic gates or other parts of the circuit) to connect to the M1 wires. Furthermore, in order to print the M2 at a pitch as tight as the CPP, it is either necessary in the lithography to tradeoff the minimum pitch that can be printed in the orthogonal direction (techniques include, for example, reticle enhancement technologies (RET) and dipole illumination) or to use multiple exposures and multiple masks, which produce a cost and yield penalty. Thus, a wrong way M2 solution has limitations that extend throughout the entire design and compromise the ability to route with high density to M1 wires or the processing cost and yield of the product.
Yet another possible solution is to add a head (or flag) to the gate to transpose the gate connection and allow increased layout density. The contact can then be placed directly over (squared on) the head. Using the head, however, increases the deviation in gate width. This deviation in gate width increases the variation of the critical dimensions and can pose yield and reliability problems.
Thus, there is a need to increase the layout density by allowing M1 vertical wire routing while minimizing development and process costs and maintaining performance and reliability at desired levels. The denser layout with the M1 vertical wire routing may lower product cost and/or increase operating speed of a chip utilizing the denser layout. Such a denser layout may be useful in advanced technologies such as 22 nm technologies to produce faster and more reliable CPUs (central processing units) or GPUs (graphical processing units).